shareability attribute for armv8 cortex a-53

Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
MOESI state encoding of Cortex-A7

Hi, I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory" we can see several information regarding a cache line. Those are: 1. Current data in cache 2. its 4-bit MOESI state, 3. Outer Memory...
How to flush write buffer when memory attribute is normal_nc

Hi, I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue. When I write data(4 bytes aligned) to pcie bar with ioremap_wc...
Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
Cache cleaning and invalidating in ARM Cortex-A

Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two...