TTBR1 translation fault when using an identity mapping

Hello everyone, I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3...
Trouble configuring MMU for 2MB block mapping

So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...
Different between AF vs AP (MMU Setup)

What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
Disabling the MMU

Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
How to design simple memory protection using MMU attributes & modes ?

Hello, Can anyone give some points as to how to design simple memory protection model, of standalone OS application composed tasks, each has its own region/section with attributes such as read only...