• hi. i wonder AMBA 3.0 AXI out-of order - WID & RID
    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI. Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading. Firstly, i very wonder...
  • axi problem
    Hi All I have two questions. Q1: is it ok that WVALID , WREADY and BVALID assert at the same cycle? Thanks! Q2: what is different between out of order and data interleaving ? Thanks!
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • ARMv8 memory ordering
    In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code: AArch32 Px PLDW[R1] ; preload into cache in unique state Loop...
  • GIC order of completion of interrupts
    Hello, Reading the "ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification" I read that "For nested interrupts, the order of interrupt completion must be the reverse of...