• AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • axi ordering
    Hi the master is connected to axi-interconnect and two slaves(A and B) are connected to axi-interconnect. The master send a write transcation(AA) to slave A and then send a write transcation(BB) to slave...
  • AXI narrow transfers
    I would appreciate assistance on the following: Suppose a bus master with 128bit data width. This master access a 64bit slave via AXI matrix as follows: awaddr = 0x4000_909F awsize = 0x0 (8bit write)...
  • AXI Write data interleaving
    Hello Everyone, [ This not specific to AXI3/4 ] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases...
  • AXI Atomic Access
    Hello, I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion. My question is: 1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates...