• Arm Cortex-A8 program flow prediction
    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code: char SecretDispatcher[256 * 512]; int counter = 0; //evicting SecretDispatcher from cache...
  • Question about program flow prediction
    I am examining ARM Cortex-A8 program flow prediction abilities, in document of Cortex-A8 arm specified that it would predict LDM instruction with PC in register list. now i have a question, if we have...
  • ARMv7 Branch Prediction Enable
    On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed: ... @ Invalidate TLB MCR  p15, 0, r1, c8, c7, 0 @ Branch Prediction Enable MOV r1, #0 MRC p15, 0, r1, c1, c0, 0     @ Read Control...
  • Out-of-Order of Cortex-A15 core and an interrupt
    I would like to know an behaviour of the interrupt on out-of-order. In-order situation :  The interrupt is issued at once because the instruction that is not completed is discarded. Out-of-Order situation...
  • Interrupt on Out-of-Order pipeline of Cortex-A15
    Hi, I would like to know the interrupt behavior on Out-of-Order pipeline on Cortex-A15. When some instruction is executing on Out-of-Order pipeline, one interrupt is happens. In this case, its interrupt...