• NEON pipeline stages in instruction timing
    Note: This was originally posted on 3rd April 2012 at http://forums.arm.com I'm trying to understand more detail about the instruction timing in Cortex-A8/A9. In TRM of A8, the timing is described as...
  • pipeline result register write.
    Note: This was originally posted on 13th January 2011 at http://forums.arm.com Hi. I'm trying to develop a small program to count the cycle of a program. I found an interresting case. As you know 2 instructions...
  • Compilation stages of ARM in Keil
    can anyone tell me the step-by-step generating file while compiling in keil...and why it is creating .htm file. plz hlp me
  • Pipeline Structure
    Hello, Anyone has ideo how Assembly language can be used to determine the inner Pipeline Structure of ARM Core Platform. Don't know detail of the ARM Core. Thankyou
  • Read and Write
    Hi Since I want to set three input and one output so my code would be like that: //Configurations sbit READ_1=P1^0; sbit READ_2=P1^1; sbit READ_3=P1^2; sbit SEND=P1^3; READ_1=1; //INPUT...