• Disabling D-Cache
    Note: This was originally posted on 3rd August 2009 at http://forums.arm.com I use the following instructions void disable_cache() {   asm(" MRC P15, #0, R0, C1, C0, #0 ");   asm(" MOV R2, #4        ...
  • Cortex M3 Cache disable
    Note: This was originally posted on 23rd August 2010 at http://forums.arm.com Hi everybody, I have here an STM32F103ZE with an Cortex M3 core and I need to disable the cache. But unfortunatly I dont find...
  • Problem disabling cache on ARM926ej-s
  • Problem disabling cache on ARM926ej-s
    I've been using mmu.c to setup my MMU table and enable the caches - for months now, so I think that part is OK. Now I need to disable the icache, dcache and mmu, do some stuff and re-enable them...
  • Why Cache L1 Counters disable on Streamline
    Hello every one, ARM DS-5 (University) streamline to read counter events from Beagle Bone Black board. for some reason i can not get the l1Caches counter to work. Any Advice? Thanks