• NEON pipeline stages in instruction timing
    Note: This was originally posted on 3rd April 2012 at http://forums.arm.com I'm trying to understand more detail about the instruction timing in Cortex-A8/A9. In TRM of A8, the timing is described as...
  • Calculating L1 hit latency and L2 hit latency
    Note: This was originally posted on 16th January 2012 at http://forums.arm.com All, I am new here. I was interested in measuring the L1 hit latency for A15/A9. Which signals do I need to probe inside...
  • APB register latency on lpc24xx
    I am trying to achieve a low latency PWM interrupt routine and cannot achieve fast register access times to any APB peripheral using the document " Getting top performance from NXP's LPC processors...
  • Any equivalent NEON instruction to SMULWy?
    Note: This was originally posted on 6th July 2013 at http://forums.arm.com Hi everybody, I'm currently working on 7x7 gaussian blur filter for NEON. And since everything bigger than 3x3 is hard to handle...
  • NEON instructions for fixed-point arithemtics
    Hi, I'm somehow familiar with NEON, but it's the first time I'm trying to get serious advantage from it. I have fixed-point code which does very best from armv7 ISA. In particular it uses instructions...