• dissable interrupts with CPSR
    Note: This was originally posted on 19th June 2009 at http://forums.arm.com Hi, this regards the ARM 7 core. In the CPSR register I can set the "I bit" to dissable the "IRQ interrupts" But which all interrupts...
  • can't read CPSR correctly
    Note: This was originally posted on 15th October 2009 at http://forums.arm.com hello, I write the following codes to determine the mode in which the processor(Xscale) operates: int x;     asm volatile...
  • SAM7X IRQ interrupt entered with CPSR=0x60000013 (supervisor mode) !?
    Hello. I'm converting (another persons) code from another IDE to KEIL uV4 (no RTOS). When running the code, the 1st PIT-interrupt (ISR_Pit) is entered with: - CPSR=0x60000013 (supervisor mode)...
  • Flags of APSR Register in Cortex M3
    Note: This was originally posted on 19th April 2011 at http://forums.arm.com Hello all, I am having probelm in writing Flags of APSR Register in Cortex M3. The result of a comparison cuases the negative...
  • event flag
    what are the definitions of each event flag bits