I am TF-a newcomer.I would like to ask about ATF related questions.

1.How is the exception level of armv8 created for initialization?It seems that only the initialization of el3 is available here？ 2.Is there any way to implement multi-core boot in BL phase (for multi...
CA57中所有Core共享一个GIC CPU interface?

hi, experts: CA57 MPCore TRM中： Page 1-7 : Note: All the processors share an integrated L2 cache and GIC CPU interface. 根据Page 2-2 CA57's block diagram: 每一个Core，都有自己的GIC CPU Interface. 因此，CA57 MPCore中...
如何理解Cortex-A57只包含GIC CPU Interface？

hi, experts: CA57 TRM说：它只包含GIC CPU Interface。请教2个问题： 1. CA57的SOC，需要另外集成GIC-400 IP吗？ 2. GIC-400里的GIC CPU Interface会和CA57的各个Core对应的GIC CPU Interface连接吗？ best wishes,
如何理解Cortex-A57只包含GIC CPU Interface？

hi, experts: CA57 TRM说：它只包含GIC CPU Interface。请教2个问题： 1. CA57的SOC，需要另外集成GIC-400 IP吗？ 2. GIC-400里的GIC CPU Interface会和CA57的各个Core对应的GIC CPU Interface连接吗？ best wishes,
CA57中所有Core共享一个GIC CPU interface?

hi, experts: CA57 MPCore TRM中： Page 1-7 : Note: All the processors share an integrated L2 cache and GIC CPU interface. 根据Page 2-2 CA57's block diagram: 每一个Core，都有自己的GIC CPU Interface. 因此，CA57 MPCore中...