• In Arm v7 mmu, stage2 translation cannot use short descriptors. WHY?
    ARM V7 document states: "In ARMv7-A short descriptors only be used at EL0 and EL1 stage 1 translations. They cannot, therefore, be used by hypervisors or Secure monitor code." Why stage2/hypervisors...
  • Count Main TLB miss
    Hello, experts: My platform is a Cortex-A9 MPCore CPU, Sabre Lite(i.mx6). I tried to count TLB miss so I implemented PMUEVENT to check micro TLB miss. But PMUEVENT doesn't support the main TLB miss...
  • AArch64 TLB maintenance requirements
    Hello all, I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem. The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order...
  • TLB Conflict abort
    Hi All, I want to check TLB Conflict abort. How can I create an address which matches multiple entries in the TLB as ARMv8 spec mentioned. ARMv8 spec: "An address can hit multiple entries in...
  • Cortex-A9 TLB lockdown
    Hello, expert. I tried to implement TLB lockdown in Cortex-A9. Cortex-A8 and ARM1136JF RFP offer detailed TLB lockdown method but cortex-A9 RFP doesn't offer it. I tried TLB lockdown following Cortex...