• Cortex-M0+ hangs on return
    During debugging the Cortex-M0+ (ATSAMR21G18) all of a sudden hangs. Stack looks fine. LR contains the correct return address (odd), which based on the BX instruction description ( http://www.keil.com...
  • DMB, DSB, ISB instructions
    Can anyone explain in simple english when these instructions must be used. I have read the manuals and have some kind of idea, but obviously my english skills are not good enough to fully understand...
  • What is the difference of DMB and DSB instruction?
    Dear sirs, From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which...
  • dsb and dmb
    Hi all: I have some questions about DMB and DSB in armv8. (1) In armv8 Reference Manual doc, it says " The DMB instruction does not ensure the completion of any of the memory accesses for which...
  • The difference between DSB and DMB instructions of ARM1176JZF-S
    Note: This was originally posted on 30th September 2011 at http://forums.arm.com Dear Sirs,         I am currently testing a comstomized SOC with ARM1176JZF-S core, 32KB-cache on Linux-2.6.31.2, and I...