• Cortex-M0 DesignStart Eval
    Hi I have download the Cortex-M0 DesignStart Eval file (AT510-MN-80001-r2p0-00rel0), and read the ARM FPGA board (MPS2+) datasheet. The MPS2+ have many peripheral devices but we don't need it, so...
  • Does the DesignStart FPGA Cortex-M1/M3 support SWD multi-drop?
    I am instantiating both a Cortex-M1 and a Cortex-M3 in a Xilinx 7-series FPGA and need SWD access to both cores. Do these cores support SWD multi-drop? If so, is there a reference design - or just any...
  • Cortex-M0 DesignStart R2
    For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea...
  • does ARM Cortex-M0 DesignStart support SWD debugger?
    I am studying the ARM Cortex-M0 DesignStart. I found there are debug port SWDIOTMS and SWCLKTCK in the port list of cmsdk_mcu.v, and there are CPU options which defines the CPU's feature. I configured...
  • SWD issue in Cortex-m0
    We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside), we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex...