Cycle model build issue - ../../../../cortexm3_rtl

make compile SIMULATOR=ius DSM=yes xmvlog: *W,NOTIND: unable to access -INCDIR ../../../../cortexm3_rtl/logical/cm3_tpiu/verilog (No such file or directory). Fails because cortexm3_rtl/ is not present...
Cycle model build issue - ../../../../cortexm3_rtl

make compile SIMULATOR=ius DSM=yes xmvlog: *W,NOTIND: unable to access -INCDIR ../../../../cortexm3_rtl/logical/cm3_tpiu/verilog (No such file or directory). Fails because cortexm3_rtl/ is not present...
Cycle Models license

I have received the PSN and followed the Step-by-step guide. Then I got the license.lic file and created ARMLMD_LICENSE_FILE environment. But I cannot pass the HELLO TEST simulation with Cycle Model ...
Cycle Models license

I have received the PSN and followed the Step-by-step guide. Then I got the license.lic file and created ARMLMD_LICENSE_FILE environment. But I cannot pass the HELLO TEST simulation with Cycle Model ...
Inconsistency with ATPG model / Verilog-Sim model

Hi All, I am having trouble with the Tetramax-ATPG simulation. I am designing a TSMC 40nm SoC and am using the IO library provided by ARM. ATPG and Verilog-Sim models are provided. I am creating...