• Cortex-A7 burst transaction question
    hi, experts: 我想在CA7 平台上,使用 LDMIA / STMID to produce some continual burst memory transactions. CA7的DCache line = 64bytes(512bit) 因此,如果我确保访问的目的地址,是64bytes对齐的,那么就会产生burst memory transactions,对吗? 比如: LDMIA...
  • ARMv8中的Non-cacheable transaction
    在CA53的TRM中,关于ACE transfer有以下描述 For Non-cacheable transactions: • INCR N (N:1, 2, or 4) 128-bit for write transfers. 想请教一下,CPU中执行什么样的指令,会在总线上产生 INCR4 128bit的write transfer 多谢!
  • LDP/STP burst transaction question in ARMv8
    hi, experts: 在ARMv8中:使用LDP/STP,取代了LDM/STM 在ARMv8中:可以使用 LDP / STP to produce some continual burst memory transactions. CA57的DCache line = 64bytes(512bit) 因此,如果我确保访问的目的地址,是64bytes对齐的,那么就会产生burst memory...
  • Memory Protection Unit -R7
    各位专家,您好! 我enable R7的MPU后,发生软件跑飞的情况,不知道怎样入手调试。麻烦各位专家指导下,谢谢! 调试信息如下: /* Now we can safely enable the MPU in SCTLR register. */ mrc p15, #0, r0, c1, c0, #0 orr r0, r0, #MK_MPU_ENABLE dsb ...
  • Store PC to different from memory and register?
    I,m using keil uVison4.22 and the device is arm7 ,I am testing about SubroutineCall,but found a doubt that the code store the r15(PC) to the address r13 of memory,and the value is PC + 12 ,if i use mov...