Any advice on running 180nm ROM/RAM compilers on modern Linux?

Hi I'm trying to run 180nm ROM/RAM compilers and the OS options are very restricted, the ROM compiler requirement is SunOS5 I've got a Linux platform. I'd appreciate advice on where I should focus...
Cache in SOCs

Dear Sir/Ma'am, In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. I know processors...
You’ve talked about A75 system guidance today, what is next?

This question was asked in the ' How to optimize a system with the latest ARM DynamIQ processors' webinar . You can view all other related questions in this blog post .
Cortex M series and their compatibility

Hello , I am new to ARM. I have a particular software package written to the Cortex M0+ MCU. How can I evaluate that these libraries will be compatible with other type of cortex M series microcontrollers...
CPUIdle Marvell SoC

Hello, I'm facing an issue with some of the linux kernel code. I'm trying to use the CPU suspend fonction (located in arch/arm/kernel/sleep.s) of the linux next kernel The code is the following: ...