ARM-A15 SoC integration for Simulation (VCS) How to Enable traces for debug

Hi, I owe ARM-A15 integration and verification to our SoC simulation using VCS tools. I have no visibility or any way to track down the ARM Program counter for debug. Is there any ARM verification...
Cache in SOCs

Dear Sir/Ma'am, In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. I know processors...
CPUIdle Marvell SoC

Hello, I'm facing an issue with some of the linux kernel code. I'm trying to use the CPU suspend fonction (located in arch/arm/kernel/sleep.s) of the linux next kernel The code is the following: ...
Import SOC design in eclipse

I have design SOC in system canvas . its build successfully on ISIM and cadi target but when I import in DS Eclipse it shows error I am adding.exe file
AMP Baremetal on SoC using Terasic DE1-SoC Computer system?

I have a Terasic DE1-SoC with the implimented Computer system. Can someone give me a step by step process to run two separate binaries on both A9 cores using baremetal with AMP configuration? One processor...