AXI

What is byte lane in AXI?
Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior

Hi, The AMBA5 spec for ACE5 shows some new signals versus ACE4 : VAWQOSACCEPT VARQOSACCEPT AWAKEUP ACWAKEUP SYSCOREQ SYSCOACK How are these used in an SOC system ? For example, I think...
How did you measure the Instruction cache efficiency? Just code execution from Flash? Reading data from Flash? Programming data to Flash?

This question was raised in the ' How to implement a secure IoT system on ARMv8-M ' webinar, view all the questions in the round up blog post .
STM(System Trace Macrocell)

Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ? what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format...
design a low cost (under $300) system

tracking people in the video stream. The system will be installed overhead to get a top view of the people it is tracking. The output of this system are the x, y positions of the people in the video image...