CHI protocol cache line states

The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...
Why I can't find the TRM of PL301 in Infocenter

Only PL300 can be searched . Where can I get the TRM of PL301 , not Technical Summary ?
How does nic400 directs traffic from master to slaves?

How does nic400 directs traffic from master to slaves? e.g. Master A, Slave B, ad Slave C are connected to NIC400. Master A can send traffic to Slave B and Slave C. Address used for these transaction...
CHI/ ACE-Lite Interface

I have a custom accelerator to be integrated with Corelink CMN-600. The CMN-600 has a CHI/ ACE-Lite Interface. How can I add a CHI/ ACE-Lite Interface to my custom accelerator? Is there a tool which can...
Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior

Hi, The AMBA5 spec for ACE5 shows some new signals versus ACE4 : VAWQOSACCEPT VARQOSACCEPT AWAKEUP ACWAKEUP SYSCOREQ SYSCOACK How are these used in an SOC system ? For example, I think...