JTAG/SWD and entering debug monitor

How does a JTAG/SWD debugger know when BKPT is executed? My guess is that BKPT triggers entry to debug monitor and entering debug monitor sets something in the debug port, but what, and how does a debugger...
Funny PABT behaviour - why?

I came across a weird behaviour when trying out my program on Raspberry Pi 2b (Cortex-A7): When I try my PABT-handler using BKPT, the handler is entered fine, but on return the program restarts. The restarted...
Why AXI4 changed the definition of AxCACHE?

Hi, In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate. But is there any concrete reason for this change? Actually...
why there is no split or retry responce in AXI ?

In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?
why are there no schematic view of standard cell

Recently downloaded 65nm Arm standard cell libraries, I see symbols and layouts, but no schematic view. How can one LVS when there is no schematic of the standard cell. Also, how can run a spectre simulation...