ARM Linux: Can I control cache flush and invalidation in user space?

These days I'm using Xilinx SoC to design a software, which shares memory between Cortex-A cores and FPGA. I've tried reserve memory in Linux and mmap() /dev/mem. The problem is if I use O_SYNC, it very...
How can I use imx6 in Asymmetric (***) mode?

I would like to use iMX6 in asymmetric mode (Windows EC7 + Linux). Is that anyhow possible? Marco
ATF design

Hello All, i need to modify in ATF code, i found the documents in github project but it didn't cover many thing in code, so is anyone have document talk more about ATF design and code ?
can i use QNX Neutrino RTOS with cortex-m3

I have seen that lot of arm boards are having qnx rtos but all were like cortex-a or cortex-r ,but the soc i have is having cortex-m3 ,so before investing lot of time in this os ,i want to be sure whether...
I want to learn RTOS in ARM Cortex-M Processors.

Hi, I wanted to start learning RTOS in ARM Cortex M Processors. I currently work on Cortex M0 IC provided by Nuvoton where I use the BSP to get things done. Now I need to move a step ahead and start...