Request for advise on better ARM learning path for VLSI engineer

I am a experinced VLSI/ASIC logic design engineer living in Israel who wants to educate himself FPGA design with embedded ARM on the private basis. Please, advise on the better path how to do that. For...
design a low cost (under $300) system

tracking people in the video stream. The system will be installed overhead to get a top view of the people it is tracking. The output of this system are the x, y positions of the people in the video image...
AHB lite single master single slave

I have completed the material provided by arm, can i plz have a simple code of single master and single slave in ahb_lite protocol for better understanding?
HTRANS for HBURST == SINGLE

Is HTRANS always NONSEQ for SINGLE bursts? I imagine this is ok: A0 A1 A2 NONSEQ NONSEQ NONSEQ SINGLE SINGLE SINGLE I imagine this is not ok (?): A0 A1 A2 NONSEQ SEQ SEQ SINGLE SINGLE SINGLE
single burst in ahb lite

HI I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not. If i am using a write based read ,The write is not complete due to wait at the time ,At...