Compare the performance of In-order and Out-of-order in AXI protocol

I am checking the performance of an SoC system. Currently, I am facing an issue as below: I have 1 master access to 1 slave (OS = 8). Assume that I have 3 packages: A0 (ID = 0), A1(ID = 1), A2...
what action will be performed by the master based on the read and write responce in axi 4?

i read the specification of AXI 4 protocol. i want to know what action will be performed by the master when it receive okay,exokay,slverr or decerr. okay and exokay says that the transfer is completed...
How AHB Arbiter should handle granting bus masters while performing only a SINGLE transfer?

Suppose A master wants to perform a SINGLE transfer. Consider the waveform in fig below. As depicted in the waveform. Master 1 is requesting bus at T1, arbiter samples request and drives the grant...
BUSY transfer and WAIT state both are using the same time ,How to perform the AHB?

Hi sir, T1=NON-SEQ T2=BUSY T3=SEQ T4=SEQ T5= SEQ This is for WRITE operation: i am using a BUSY state for T2. Then my WAIT state for till T3. I have read from the forum if WAIT state u are...
You mentioned Quality of Service, how do ARM systems optimise performance for real-time masters?

This question was asked in the ' How to optimize a system with the latest ARM DynamIQ processors' webinar . You can view all other related questions in this blog post .