How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 4

By William Orme, Strategic Marketing Manager, Arm and Nick Heaton , Distinguished Engineer, Cadence This is Part 3 of a 4 part series. Links below Part 4 Cadence Interconnect Workbench We have...
How to Measure and Optimize the System Performance of a Smartphone RTL Design - Part 2

By William Orme, Strategic Marketing Manager, Arm and Nick Heaton , Distinguished Engineer, Cadence This is Part 2 of a 4 part series. Links below Part 2 Performance Characterization Because of...
How to Measure and Optimize the System Performance of a Smartphone RTL Design

By William Orme, Strategic Marketing Manager, Arm and Nick Heaton , Distinguished Engineer, Cadence This is Part 1 of a 4 part series. Links below Part 1 Introduction The evolution of today’s...
CoreLink NIC-400: a great interconnect for wearables and entry-level smartphones

As the number of processors and I/O masters in an SoC continues to rise the need for an efficient and easy to design interconnect becomes critical. An interconnect must provide sufficient throughput an...
Exploring the ARM CoreLink™ CCI-500 performance envelope – Part 2

Introduction In Part 1 of this blog series (found here ) we introduced the ARM CoreLink TM CCI-500 Cache Coherent Interconnect and described some of the new configurable features which are available over...