• Simulating the Arm Scalable Vector Extension with gem5
    Co-authored with Giacomo Gabrielli and Jose Joao The Arm Scalable Vector Extension (SVE) is a key technology for Arm processors to efficiently address the increasing computation requirements of future...
  • Running Trusted Firmware-A on gem5
    Security is increasingly becoming more relevant, as the vulnerability surface grows along with the number of connected devices. Arm has prioritized security for many years, introducing TrustZone® as a...
  • Concurrent Programming, Transactions and Weak Memory
    This is the first in a two-part post from Arm Principal Researcher Dr Nathan Chong on his joint research with Tyler Sorensen (Imperial College London) and Dr John Wickerson (Research Fellow, Imperial...
  • The Semantics of Transactions and Weak Memory in x86, Power, Arm, and C++
    This is the second in a two-part post from Arm Principal Researcher Dr Nathan Chong on his joint research with Tyler Sorensen (Imperial College London) and Dr John Wickerson (Research Fellow, Imperial...
  • The Arm Scalable Vector Extension (SVE)
    Published in IEEE Micro, Vol. 37, Issue. 2 Authors: Nigel Stephens, Stuart Biles, Matthias Boettcher, Jacob Eapen, Mbou Eyole, Giacomo Gabrielli, Matt Horsnell, Grigorios Magklis, Alejandro Martinez,...