• Mapping of AXI cache with AHB5 prot

    Manasa Avula
    Manasa Avula

    Hi,

    We see the mapping of AHB5 prot signal with AXI cache signals given in the table in

     http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.101375_0000_00_en/bct1529512318797.html

    It is seen that the mapping here is given with respect to AXI5…

    • over 3 years ago
    • Support forums
    • Architectures and Processors forum

  • Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification

    Pandey
    Pandey

    Hi,

    As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…

    • Answered
    • over 4 years ago
    • Support forums
    • Architectures and Processors forum