ARM instruction set pseudo instructions

Does anyone know if there is a list of ARM instruction set pseudo instructions? Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and another list...
ARM/THUMB instructions that change execution path?

Has anybody come across a list of ARM & THUMB instructions that cause deviation from the linear instruction stream? I've been trying to figure out gdb-stub single stepping using software interrupts, and...
LDR Instruction

Note: This was originally posted on 5th November 2008 at http://forums.arm.com Hi all, I am new to the thumb-2 instruction set. In one of my sample code I noticed a instruction LDR r0...
How to access the memory mapped debug registers?

Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR...
Turning on MMU and caches on Cortex-A7?

In my little program (rpi_stub) it's time to turn on MMU and caches. Most of it I seem to have hold of, except cache invalidations. In multicore situation (rpi_doesn't support yet, but maybe later...