Conflict, Register offset of GPIOx_BSRR of STM32F0x1/STM32F0x2/STM32F0x8

Dear friends, Register offset of GPIOx_BSRR is shown as 0x18 (which looks to be true) in ST's Reference Manual (p163, en.DM00031936) while it is shown as 0x1A in "stm32f072xb.h" header file. It seems...
STM32F103 and FTDI problem.Terminal doesn't transmit to FTDI

Hi friends ,I encountered a problem with serial terminal and ftdi.Let me explain. Stm32f103 is sending data to Ftdi and Ftdi is sending this data to serial terminal and I can see data, but I couldn't...
Debugging a Cortex-M0 Hard Fault

There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg niallcooling 's Developing a Generic Hard Fault handler for Armv7-M also: http://supp.iar.com/Support/?Note=23721 https...
IP Camera interface via STM32

Hi all, I am looking for developing an IP camera based system based on STMicroelectronics STM32. The way it is supposed to work is: STM32F4 will have few IP cameras connected to it. It may have...
Where is M4 hardware breakpoint address?

Hi I'm learning cortex m4 debug feature, I'm using stm32f407 discovery with openocd in ubuntu I'm trying to understad breakpoint feature, I can set breakpoint address in openocd and chip will stop...