Data during AHB Busy state

Hi everyone, I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave: TIME: T1 T2 T3 T4...
Burst termination with BUSY transfer on AHB

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

I am a Digital Verification Design Engineer. Currently, I am in the process of developing an UVM Test Bench for AHB 2.0. I have following questions. 1) From AHB Master side, Can BUSY cycles be inserted...
AHB frequency

Note: This was originally posted on 6th January 2009 at http://forums.arm.com Hi Friends, My doubt is : what is the maximum AHB clock frequency ? Regards, P.Vignesh Prabhu
AHB Arbiter

Note: This was originally posted on 21st November 2008 at http://forums.arm.com Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?