How can I do profiling in DS-5 without hardware

Dear all

How can I do profiling in DS-5 without hardware platform.

and another question :

Why in RVDS 4.1 we had this feature (profiler utility + RTSM model) but in  DS-5 it seems this feature is canceled !

Does this feature in RVDS 4.1 have problems that is discontinued in the DS-5?

  • Hi,

    There's a similar thread here that addresses your question:

    Can DS-5 Streamline be used with RTSM/Fixed models for cortex-A53 processors?  If it is possible, what is the procedure ?

    Fast Models only partially implement the PMU that Streamline relies on to gather data. Also, Fast Models are functional, rather than cycle accurate and since Streamline is a sample-based profiler, it's very questionable as to whether your results would be useful.

    In DS-5 we decided to concentrate on Streamline as our profiling tool because for complex, multicore systems, sample-based profiling is more appropriate.

    Hope this helps,


  • In reply to Joe Alderson:

    Thanks Joe,

    but as I know, in RVDS 4.1 we can do profiling  using RTSM model, what about the results of that method? Are they incorrect?

  • In reply to Mehdi:

    Hi maminian,

    Yes, RVDS can do profiling on a model, and the results are correct, but can be misleading. I can explain this in a bit more detail.

    A Fast Model simulates instructions, but does not have a measure of "time". The profiling reports generated by RVDS are accurate in the sense that the profiling reports show accurately how many times the processor has executed an instruction, a function or a certain call path. The reason why this is misleading is that most people expect a profiling tool to show how much time the processor has spent on an instruction, function or call path. The reason why how many times and how much time are different is the fact that on real hardware some instructions may execute in 1 cycle or less (e.g. backwards branch hitting the cache) while others can take tens or even hundreds of cycles (e.g. data access that misses the cache and TLB and has to wait for a higher priority master to finish a previous memory access).

    Because of the complexity of new SoCs we decided that the technology in the RVDS Profiler connection to models was no longer suitable for new designs, so we decided to not take forward this product into DS-5. In DS-5 we replaced the Profiler with:

    * Streamline: a more appropriate technology for Linux and Android and complex SoCs, based on kernel trace and PMU counters

    * A simpler trace view in the debugger, with basic profiling features. Today this trace view works on hardware only (using ETM/PTM trace), but we are already working on a trace connection to models that will give you similar (albeit reduced) functionality to what you have today.

    Best regards, Javier