arm pmu returns either zero or nearly max value

Hello,

i compiled a functioning kernel object to enable arm pmu and make it accessible to the user space on a Cortex-A57.
I am calling a function doing the following:

1) fill pmevtyper[0..5]_el0 with (masked) L1 cache event IDs
2) enable pmevcntr's with pmcntenset_el0
3) zeroize overflow register and pmevcntr's
4) *** run benchmark ***
5) read results from pmevctnr's and check overflow register
6) disable used PMU counters

i am currently counting following events:

L1I_READ_REFILL 0x001
L1I_READ_ACCESS 0x014
L1D_READ_ACCESS 0x40
L1D_WRITE_ACCESS 0x41
L1D_READ_REFILL 0x42
L1D_WRITE_REFILL 0x43

now, the counters sometimes return plausible values, but most of the time they return zero or a high number in the range ~ 4294967284-4294967295 with no overflow bit set. 4294967295 means all 32 bits of the pm are set and it confuses me how often it reaches that value in contrast to all the times the counters return zero.
The problem does not occur with L1I_READ_REFILL 0x001 and L1I_READ_ACCESS 0x014,
but it also occurs with:

L2D_READ_ACCESS 0x50
L2D_WRITE_ACCESS 0x51
L2D_READ_REFILL 0x52
L2D_WRITE_REFILL 0x53

am i using the performance counters wrong?