Please refer to the following guide to add the HiKey 960 config database into DS-5:
Guide to adding HiKey 960 configuration database to DS-5
Download HiKey 960 configuration database
1. For A53 cluster:
for i in 0 1 2 3; dofor j in 0 1 2 ; doecho 1 > /sys/devices/system/cpu/cpu$i/cpuidle/state$j/disable;done;done
2. For A73 cluster:
for i in 4 5 6 7; dofor j in 0 1 2 3 ; doecho 1 > /sys/devices/system/cpu/cpu$i/cpuidle/state$j/disable;done;done
If the HiKey board does not already have a JTAG connector then one will need to be soldered. The JTAG interface shall use the 10 pin JTAG connector (0.05” pitch) . Please refer to the following guide for detail about 10 pin JTAG Pinout:
Guide about JTAG Pinout
The JTAG connector on the HiKey board will be:
Physical connection with DS-5:
The following connection options are available by selecting different debugger instance::
To configure debug and trace settings for your target click on the "Edit..." button in the "Connection" tab.
Now, DS-5 supports all of the trace sinks for Cortex-A53 and Cortex-A73 clusters:
After clicking "Edit..." button, the trace configuration GUI will show the following:
Since there is no Mictor 38 port on the HiKey960 board I was only able to fully test debugging the cores and tracing via ETR and ETF, excluding DSTREAM off-chip trace.
Send mail to firstname.lastname@example.org if followings do not work.
Please note that you cannot select the global ETF and ETR at the same time, as global ETF cannot be as ETB and ETF at the same time(When you select ETR trace sink, the global ETF will be as ETF, can not be the trace sink ETB).
Now you will see different trace sinks can work together: