DS-5 support with the HiKey 960 board

DS-5 Debugger helps you get to the root of software bugs throughout your development process. From device bring-up to application debug, it can be used to develop code on virtual platforms and hardware to help you get your products to market ahead of the competition. How can you make DS-5 work on HiKey 960 board? It is very easy!!

Step 1: Add the attached HiKey 960 configuration database into DS-5

Please refer to the following guide to add the HiKey 960 config database into DS-5:

Guide to adding HiKey 960 configuration database to DS-5

 Download HiKey 960 configuration database

Step 2: Disable CPUIdle by the following script in the serial console if linux kernel boots up

1. For A53 cluster:

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for i in 0 1 2 3; do

for j in 0 1 2 ; do

echo 1 > /sys/devices/system/cpu/cpu$i/cpuidle/state$j/disable;

done;

done

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2. For A73 cluster:

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for i in 4 5 6 7; do

for j in 0 1 2 3 ; do

echo 1 > /sys/devices/system/cpu/cpu$i/cpuidle/state$j/disable;

done;

done

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Step 3: Connect the HiKey 960 board with DS-5 by JTAG

Attach JTAG connector

If the HiKey board does not already have a JTAG connector then one will need to be soldered. The JTAG interface shall use the 10 pin JTAG connector (0.05” pitch) . Please refer to the following guide for detail about 10 pin JTAG Pinout:

Guide about JTAG Pinout

The JTAG connector on the HiKey board will be:

JTAG connector on the HiKey board

Connect with DS-5

Physical connection with DS-5:

Physical_5F00_connection

The following connection options are available by selecting different debugger instance::

  • one core(Cortex-A53_x or Cortex-A73_x),
  • single cluster(Cortex-A53x4 SMP or Cortex-A73x4 SMP)
  • two clusters(Cortex-A73/Cortex-A53 big.LITTLE)

selecting different debugger instance

Step 4: Enable trace functionality if you want

To configure debug and trace settings for your target click on the "Edit..." button in the "Connection" tab.

Edit_5F00_button

Now, DS-5 supports all of the trace sinks for Cortex-A53 and Cortex-A73 clusters:

  • ETR: System Memory Trace Buffer (CSTMC_0/ETR), this can be used by both clusters
  • Global ETF: On Chip Trace Buffer (CSTMC_1/ETF_Global), this can be used by both clusters
  • Private ETF: On Chip Trace Buffer (CSTMC_2/ETF_A53), Cortex-A53 cluster private ETF
  • Private ETF: On Chip Trace Buffer (CSTMC_3/ETF_A73), Cortex-A73 cluster private ETF
  • Dstream: DSTREAM 4GB Trace Buffer, this can be used by both clusters.

After clicking "Edit..." button, the trace configuration GUI will show the following:

A53_5F00_trace_5F00_enable

A73_5F00_Trace_5F00_Enable

Please contact Arm support if the following does not work:

Since there is no Mictor 38 port on the HiKey960 board I was only able to fully test debugging the cores and tracing via ETR and ETF, excluding DSTREAM off-chip trace.

Send mail to support-sw@arm.com if followings do not work.

Connect Cortex-A53 cluster Only:
  • A53_ETF works
  • Global_ETF works
  • ETR works
Connect Cortex-A73 cluster only:
  • A73_ETF works
  • Global ETF works
  • ETR works
Connect both Cortex-A53 and Cortex-A73 clusters
  • A53 use ETR, A73 use A73_ETF, works
  • A53 use ETR, A73 use Global ETF, works
  • A53 use ETR, A73 use ETR works.
  • A53 use Global ETF, A73 use A73_ETF, works
  • A53 use Global ETF, A73 use Global ETF, works
  • A53 use A53_ETF, A73 use A73_ETF, works
  • A53 use A53_ETF, A73 use Global ETF, works
  • A53 use A53_ETF, A73 use ETR works.

Please note that you cannot select the global ETF and ETR at the same time, as global ETF cannot be as ETB and ETF at the same time(When you select ETR trace sink, the global ETF will be as ETF, can not be the trace sink ETB).

Now you will see different trace sinks can work together:

Different trace sinks work together

Hikey960.7z
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