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SP805 Watchdog Timer

Hi,

I am writing a driver for watchdog timer for my custom platform, what I am observing is, as counter 1st time reaches to zero , then it generates an interrupt and ISR is called

  1. if I clear this interrupt in ISR then counter is reloaded and continue count down and so on and ISR would be hit next time when counter reaches zero...as it is expected behaviour
  2. If I do not clear the interrupt  watchdog should reset my system and that is not occurring, can any one help how to reset the system?
  3. If I do not clear the interrupt in ISR then interrupt will remain set and ISR continuously keep on hitting because ISR should be called continuously as interrupt is set, How I can avoid this problem as I do not want to clear the interrupt as either I want to reset the system or I would like to reload the counter at later stage outside of ISR.

Could any body help in this regard...

If you have time and want to read timer behavior from SP805 manual, it says:

."the Watchdog module is based around a 32-bit down counter that is initialized from the Reload Register, WdogLoad. The counter decrements by one on each positive clock edge of WDOGCLK when the clock enable WDOGCLKEN is HIGH. When the counter reaches zero, an interrupt is generated. On the next enabled WDOGCLK clock edge the counter is reloaded from the WdogLoad Register and the count down sequence continues. If the interrupt is not cleared by the time that the counter next reaches zero then the Watchdog module asserts the reset signal, WDOGRES, and the counter is stopped"

Also
"The Watchdog counter is reloaded from the Load Register, WdogLoad, whenever:
• the counter reaches zero
• the interrupt generation is enabled by setting the INTEN bit in the Control
Register, WdogControl, when it was previously disabled
• an interrupt is cleared by writing to the Interrupt Clear register, WdogIntClr
• a new value is written to the Load Register, WdogLoad."

Thanks in advance,

Jam