During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS)
and I got the surprise to see that the finale value of GICD_CTLR was 0x33. G1S was not enabled.
So I decided to first enable ARE S / NS, and in a second time to enable all groups, since the documentation states that switching ARE from 0 to 1 is
unpredicatable when groups are enabled.
Is this the right way to do or can I enable all 5 bits at the same time, and there is an issue with Foundation ?
Best,
V.
Hi,
It looks like you're actually running the model with a GICv2 distributor which means some of those bits are read-as-zero / writes-ignored (RAZ/WI).
If you navigate to your DS-5 installation directory and go to `/sw/models/bin/Foundation_Platform[.exe]' and run it with `--help' you'll see this:
--(no-)gicv3 enable GICv3 or otherwise use legacy-compatible GICv2 (default: GICv2)
--(no-)gicv3 enable GICv3 or otherwise use legacy-compatible GICv2
(default: GICv2)
So you need to run the model with `--gicv3'. You can do this by adding it to this box in your debug config:
Before doing this I was seeing the same behaviour as you, but now it works as expected:
x SP:0x2F000000SP:0x000000002F000000: 0x00000000memory set SP<verify=0>:0x2F000000 32 ((unsigned int) 0x00000030)memory set SP<verify=0>:0x2F000000 32 ((unsigned int) 0x00000037)x SP:0x2F000000SP:0x000000002F000000: 0x00000037
x SP:0x2F000000
SP:0x000000002F000000: 0x00000000
memory set SP<verify=0>:0x2F000000 32 ((unsigned int) 0x00000030)
memory set SP<verify=0>:0x2F000000 32 ((unsigned int) 0x00000037)
SP:0x000000002F000000: 0x00000037
So first I read the Secure GICD_CTLR register (that's what the SP: denotes), then I set the ARE_NS and ARE_S by writing 0x30 to it, then I set EnableGrp0, EnableGrp1NS, and EnableGrp1S by writing 0x37 to it, then finally I read the value back to ensure the write was successful.
Note that I've used <verify=0> because there can be a small but finite delay between the write to the register becoming visible, which can confuse DS-5 as by default it will immediately verify that writes were successful.
Hope that helps,
Ash.
Just a quick addendum to my previous reply: if you're doing this directly in code then you'll want to set the ARE_NS and ARE_S bits and then poll GICD_CTLR.RWP (bit [31]) until it's =0. This guarantees that your write the the ARE bits has completed and that its effects are visible, before you attempt to set any of the enable bits.
I am running foundation with the --gic-v3 flags, and it seems Foundation is supporting the legacy mode (because we can read 0 in GICD_CTLR at boot time).
From your answers, I think I can conclude my second approach (writing ARE_NS & ARE_S, synchro, and then write Enable bits) is the correct one and should be used, even if writing all the bit in one go might work on some devices.
Thank you !