Hi !
I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation.
- when I want to perform a synchronization, should I just wait for bit 0 (bit C) of the Cache Synchro register to be 0
or should I write 0 to it before waiting ?
- when performing a "Broadcast" operation, like Invalidate by Way, the doc states to wait for the bits in the Invalidate by way
register to be all 0's. Should I wait for Cache Synchro too ?
Best,
V.
Hi vsiles,
No, you don't need to wait for a Cache Sync. All the "Atomic" operations stall the slave port until they complete, that is to say you won't make forward progress on any other load or store (since they all necessarily go through the L2C-310) until the operation has actually finished. That includes the load for checking the Cache Sync bit..
What you DO need to do is be very careful when issuing an "Atomic" operation while a "Background" operation is in progress. So, if you do a Inv/Clean/CleanInv by Way, and then want to Sync, you must wait for the Invalidate to complete by polling the Cache Op register C bit (for whichever op you're about to do - they all read the same), first. The effect of not checking and issuing a Cache Sync while the cache is busy is a SLVERR response, which will end up as an external data abort in your Cortex-A9.
I'd personally recommend, even though it seems like using background operations would be 'faster,' performing atomic operations when you can - don't be tempted to use the "by Way" operations unless you're putting the cache in a low power state where cache RAM contents won't be retained and you need to somehow do it without blocking. It's somewhat "accepted wisdom" that a full cache clean by Way (which is a Background operation) will be faster than a sequence of Atomic operations (for cleaning a 1MiB range on a 1MiB cache, for example, you can do one register write and simply poll until it completes, vs. performing 32768 blocking operations). Unfortunately you can't do a clean *and* modify the lines in software at the same time (the TRM explicitly tells you not to, because it doesn't treat it as a hazard), which makes background operations basically pointless, and essentially puts you in a situation where you MUST poll for completion before you do anything else. Most software implementations just put a Big PL310 Lock around every cache operation so only one can be executed at a time.
Consider that if you were doing cache maintenance on L1, you'd need DSB and ISB operations anyway - the "Atomic" operations basically cover the barriers for you in a subsystem which is too far out to see the effect of an actual barrier operation, and takes away the need for other kinds of locking, or incessant polling to Device memory.
Ta,
Matt
Thank you for the very detailed answered !