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Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data

Hi there,

good morning.

I am using TMC as Embedded Trace Fifo and testing it for FULL condition.

Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF?

So that eventually it gets full setting the FULL bit in STS register.

I can see that none of the Flushing choices are enabled in FFCR register.

But still I can see that the memory is being read as soon as data is put in it.

Thus it always remains empty and I cant get it filled up completely.

Attached TRM is having one state machine on page 30 showing where all trace data can be dumped out of TMC.

But doesn't really help since the TraceCaptEn is high throughout the simulation and TMCReady bit always remains low.

And form what I understand is that while the FSM is in Running or Stopping state it already reads the date form SRAM memory.

Which is kind of bizarre and makes no sense to me.

Any help will be appreciated. The TRM on TMC is very vague and not at all helpful.

Thanks.

DDI0461B_tmc_r0p1_trm(1).pdf