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  • Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction

    Hello All,

      I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.

    When  I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?

    Scenario : Single…

  • Build more powerful SoCs from Edge to Cloud

    intelligent_flexible_cloud.pngJeff_D.jpg

    At the Linley Processor Conference earlier this week, I had the opportunity to present the challenges facing architects who are building hardware for distributed cloud intelligence. I also

    discussed how you can address these challenges with ARM’s 3…