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  • ABP wrapper/ resizer 32-128 bit FPGA SoC

    The design is implemented on a System On Chip (SoC)

    The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are sent from the processor to the FPGA fabric, and they are…

  • FPGA 嵌入ARM cortex-m0软核后,如何移植RTX

    我参考的是何宾老师的《ARM Cortex-M0 全可编程SoC原理及实现》,基本按他书上的流程都实现了一遍,但最后的RTX 的RTOS实例,他只给了软件的代码,书上只有仿真情况,我按照他上面的例程操作,就是把counter1++和counter2++换成了点LED灯和数码管,也去掉了前面的os_evt_wait_or(0x0004, 0xFFFF),下到板子后,软核还是没跑起来,所以我感觉两个地方可能有问题,一个是启动的汇编代码,是不是需要修改;还有就是是不是RTX_Config的systick是不是需要修改…

  • Segfaults for minor code changes, Alignment issue?

    I am using DS-5 w/gcc on a win7x64 to compile c++ code for Terasic's SoCKit, so x64 to arm.
    I have code that runs fine.  The first line is a cout of a string.  It then goes on to have other exciting lines.

    I add a class into the project (by dropping…

  • Is it OK to bypass all clock gates in Cortex-R52?

    Hello,

    I am doing FPGA prototyping for an SoC. There is a Cortex-R52 in the IP that needs to be prototyped on FPGA.

    I cannot close timing with all the clock gates inside R52 enabled. Can I bypass them and assign clock_out = clock_in, without affecting…

  • Meet new Arm Innovator, Adam Taylor and his top 20 resources for FPGA developers

    As embedded and IoT applications continue to grow and push boundaries, there is a need for flexibility in product designs. This has resulted in a significant growth in application-optimized designs.

    The Xilinx product portfolio has been built to enable…

  • New Research Enablement Kit: SoC Design and Prototyping

    Arm Research Enablement are pleased to announce the release of our second Research Enablement Kit: SoC Design and Prototyping.

    Arm Cortex-M CPUs are designed to meet the needs of tomorrow’s smart and connected embedded applications and are part of the…