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  • First compile, verilog files missing

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

  • "Error : REMAP is already clear" Issue.

    Hi.

    TESTNAME=bootloader test sequence is in  BP210 CM3 test sequence,

    In especially, we could find the below code,

    then we got the below error message when we ran the simulation.

    23490 ns UART: CMSDK Boot Loader 
27270 ns UART: - load flash 
45710…