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  • How can we route the interrupts to the particular core in GICv2.

    How can we route the GICv2 interrupt to the particular core ? ( I have A55 Quard core CPU )

    Do we have any example or sample code or any sequence for setting the GIC register ?

  • Armv8-M Hangs on Non-secure Interrupt Handler Exit

    Hello,

    On exiting non-secure interrupt handler, armv8-M cm33 gets in a bad state and hangs.

    I think what's happening is, on exiting non-secure handler, cpu try to restore state from a secure area, I see "sec_err_irq_mpc" fires right after non-secure irq…

  • EXTI interrupt handler not trigger for stm32f446re

    Hi,

    i'm newbie , i want to know why my code doesn't work , my coding is about external interrupt is not trigger

    EXTIx_IRQHandler not trigger for coding in the uvision5 , but the same code i'm done with stm32cobeMX that is generated is work fi…

  • How to get Interrupt number (IRQ number) during kernel panic in interrupt context?

    I have a kernel panic in the Interrupt context. I have an use case to know the interrupt service routine number (IRQ number) during kernel panic. I had look on GIC registers from register spec, I could not able to figure it out. Is it possible to find…

  • Cortex M0 Vector Table and Bootloading

    Hi guys,

    Does the M0 always default to 0x0 when an interrupt triggers? I understand VTOR is not available in M0 for relocation of the tables.

    Can I copy the application vector table just the vector table to beginning of SRAM and remap the SRAM to 0x0…

  • Cortex-M Vector Table and Address Remap

    Hi guys,

    Does the M0 always default to 0x0 when an interrupt triggers? I understand VTOR is not available in M0 for relocation of the tables.

    Can I copy the application vector table just the vector table to beginning of SRAM and remap the SRAM to 0x0…

  • A72 not handling IRQ properly

    I want a register write to happen whenever there is an interrupt at irq pin of core 0 and I have written the code for the same. A72 branches to address 0x18 (V=0 and VE=0) by default whenever there is an irq interrupt. On this instruction address, instruction…

  • Cortex-M: Does the event register only get set when an IRQ changes from not pending to pending?

    I recently had a race-condition in an application on a Cortex-M4 microcontroller, because I used a wrong order of __SEV() and __WFE() instructions to put my chip to sleep. While debugging this issue, I wondered when exactly the event register does get…

  • TM4C123 UART1_Handler

    Hi All;

    I'm using uvision compiler. Below A portion of my code regarding UART1 RX interrupt.

    I was using reading flags. I want to use interrupt.

    I didn't get an interrupt. What is wrong?

    #define UART_INT_EN *((unsigned long int *)(0xE000E100…

  • About the interrupt handling in GIC

    I am using Linaro's Android release on Juno r1 and trying to make use of performance monitor. I want to use the PMU to count each retired instruction in a specific application, however, the overflow interrupt of PMU makes me a little confused. When the…

  • GCC 7.2.1 on Cortex-M4 - C++ exceptions not being caught

    Hi all, first post.  I've posted about this issue in the NXP forums, and it was suggested I post here, since this may be a GCC toolchain issue (if it's not somehow my own fault).  If there's a better place to post this, let me know.  (I didn…

  • Debug an INVPC exception

    Hi. I have an INVPC exception that I am trying to debug on a Cortex M4 STM32. The stack contains the following values:

    0x08003555 xPSR
    0x08006824 PC
    0x08006824 LR
    0x00000000 R12
    0x08003341 R3
    0x08006824 R2
    0xFFFFFFFD R2
    0x0000FFFF R0

    The PC and LR both point…

  • how to set pendsv bit in ARM7

    i want to a very easy way of setting this bit

  • selected processor does not support `cpsid i' and `cpsie i' in arm mode.

    hi everyone,

    i'm new with ARMprocessor and dont know too much about DS-5. just alittle bit from my Softwares >>> SoC EDS 17.1 (from Altera)  - DS-5 5.28 and my OS is Windows 10. I am using DS-5 for my SoC FPGA (DE0_Nano_SoC) Altera, which…

  • To generate a FIQ from ARM GIC apart from setting GICC_CTLR.FIQEn what else needs to be configured?

    I'm just trying to generate an FIQ from GIC .All the interrupts are by default grouped to Group0 and apart from setting FIQEn trying to understand what else needs to be configured..

  • how to switch from EL3 to El1 inside u-boot before linux kernel?

    linux requires EL1,however uboot is in EL3 mode.linux is halted.

  • System call excepton handler about  the svc stack in the linux

    I am studying System call in the linux. I know that is using SVC exception handler.

    the related codes are as follow

    ====================exception handler codes===================================

    ENTRY(vector_swi)

    sub sp, sp, #S_FRAME_SIZE

    stmia sp, {r0 - r12…

  • Any Method to trigger/start FreeRTOS task from normal STM32 ISR??

    Hello Folks,

    What is the most effecient method to start a freeRTOS task only after an ISR is completed and flag or something set by ISR that triggers freeRTOS task.

    Lets take an example scenario , I have STM32F3 nucleo board in which i would like to toggle…