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  • TRACEDATA Capture issues

    Hi there,

    I am the author of the open source Orbuculum tools for SWO data parsing on CORTEX-M targets. I am currently expanding those tools by implementing 1, 2 & 4-bit parallel TRACEDATA capture from CORTEX-M3/M4 CPUs using a small FPGA connected to…

  • I am an FPGA SoC engineer and I want to create a custom SoC. Is it possible for me to learn and acquire the development flow for less than 5K EUR budget – and if so, how should I proceed?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Could you recommend a specific FPGA board for ARM Cortex-M0 and Cortex-M3 implementation?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • The Cortex-M0 and Cortex-M3 processors are free for FPGA prototyping, but are they also free for IC prototyping?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • How to implement Cortex-M3 DesignStart Eval r0p0-02rel0 to Xilinx virtex 5 board?

    Hi.

    I came across Cortex-M3 DesignStart Eval r0p0-02rel0 implementing to the boards name of  ALTERA's MPS2+ from here https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system .

    But I'm looking for Xilinx board…

  • CM3 DesignStart Build warning messages with Quartus Prime 17.0.2

    Hi,

    I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

    I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

    Critical…

  • Has anyone had problems with implementing App Note AN387 using Cortex M0 r2p0 on a Cortex-M + dev board?

    All,

    I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

    In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

  • DesignStart Eval on Terasic DE10-Standard Board

    Hello,

    For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
    The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

    If I try to compile the ".sof" file of the Eval package in Quartus Prime…

  • DesignStart Pro: APB on FPGA via Quartus Prime

    Hello,

    I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…

  • arm cortex m3 designstart debug with st_link.

    I download arm cortex m3 prototype  to the CYCLON 5 FPGA .Then use keil to debug the software but when click he debug button ,I encountered an error like the one shown above.

    I don't know how to solve the problem 

  • How to Debug CM3 DesignStart in the FPGA

    I use the ARM Cortex-M3 DesignStart Eval on the FPGA platform, I use J-link to download the program to the system but the system is not properly implemented. I downloaded the generated Hex file via J-link to the FPGA development board via Keil. Is the…

  • How to use the microphone to input sound and store on the MPS3 FPGA

    Such as the title, I have a board of MPS3

    I want to try to use the microphone to input the sound, then output through the speaker.

    But I have been unable to find a way. I hope someone can point me out. Thank you.

  • Cortex M3 on Arty A35T with Vivado 2018.3 Windows 10

    Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…