Browse By Tags

  • FPGA Prescale register address incorrect in MPS2(+) software header file

    The FPGA prescaler register address is incorrectly defined in the header file SMM_MPS2.h

    This file is used in all Arm test software for MPS2, such as selftest, shieldtest, demo etc. The same header file is also used in MBED base code for MPS2.

    The incorrect…

  • LogicTile 20MG SMM-A57 bring up with ARM Versatile Express

    This is the boardThis is the LogicTileDVI OUTPUT

    Hi,

    Today I received my Arm versatile express board, which has only LogicTile 20MG (no other board) on it on Daughter board  2 section. I have no idea how to bring it up.

    So,

    my questions are,

    1) is there a tutorial out there which does the bring up?…

  • LogicTile 20MG SMM-A57 bring up with ARM Versatile Express

    Hi,

    Today I received my Arm versatile express board, which has only LogicTile 20MG (no other board) on it on Daughter board  2 section. I have no idea how to bring it up.

    So,

    my questions are,

    1) is there a tutorial out there which does the bring up?\

    …

  • Loading instruction set

    Note: This was originally posted on 7th October 2008 at http://forums.arm.com

    HI,
       I am trying out the Cortex M1 on an altera FPGA. I have an example implementation from the Altera kit which uses ITCM to load the software files on the ARM. I want to instead…

  • DesignStart FPGA 101: How to Design with Arm Cortex-M1

    July 11, 2019 03:00 PM to 07:00 PM Coordinated Universal Time

    GOWIN Semiconductor webinar series: Learn how to design with Cortex-M1 soft CPU IP into Gowin FPGAs Date: Thursday July 11 Times: 4pm and 8pm BST This webinar will introduce you to configuring GOWIN FPGA's with an Arm Cortex-M1 soft CPU IP, from...

  • Could MPS3 FMC connector provide more than 100 1.8V FPGA signal?

    I would like to verify some system function and need to make a daughter card which include nor flash and sram chip, and I am considering to use MPS3 as the main platform instead of my MPS2+ board.

    Total 90  I/O port (io standard is 1.8V) are required for…

  • Request for advise on better ARM learning path for VLSI engineer

    I am a experinced VLSI/ASIC logic design engineer living in Israel who wants to educate himself FPGA design with embedded ARM on the private basis. Please, advise on the better path how to do that. For example, "go to this ARM site link such and such…

  • SCP firmware for Juno board

    Hello,

    I am trying to play with the SCP on Juno board. However, I found that the source code of SCP firmware for Juno board is not included in ARM Trusted Firmware. I do get some open source SCP firmware on ARM's github, however, it seems that this SCP…

  • How can I learn to build my own computer with Arm processors?

    Hi dears.

    I am looking for a book explained how to make a computer by using Arm core processors?

  • TRACEDATA Capture issues

    Hi there,

    I am the author of the open source Orbuculum tools for SWO data parsing on CORTEX-M targets. I am currently expanding those tools by implementing 1, 2 & 4-bit parallel TRACEDATA capture from CORTEX-M3/M4 CPUs using a small FPGA connected to…

  • Bypassing all clock gates in Cortex-R52 (ARMv8)

    Hello,

    (#context): I have a Cortex-R52 in the SoC design. My team is in charge of FPGA prototyping of the entire/part of the SoC. I am prototyping (on FPGA) part of the SoC which has the R52 plus some other IPs.

    (#problem): It's not possible to close…

  • Partial Word Access to Altera Avalon Memory-Mapped Slave

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

  • Can the ARM corrupt the timing on the AXI bus

    I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…

  • Meet new Arm Innovator, Adam Taylor and his top 20 resources for FPGA developers

    As embedded and IoT applications continue to grow and push boundaries, there is a need for flexibility in product designs. This has resulted in a significant growth in application-optimized designs.

    The Xilinx product portfolio has been built to enable…

  • Cortex-M0 DesignStart processor size (FPGA)?

    Dear sirs,

    I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.

    When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.

    (I configure for using Spartan…

  • Fail to compile the ARM MPS2 FPGA project

    Hi,

    I'm trying to build the MPS2 FPGA project (unmodified, as it is supplied in the kit) and constantly getting an error message saying "Quartus Prime Software quit unexpectedly".

    It always crashes at the "Partition Merge" stage after…

  • I am an FPGA SoC engineer and I want to create a custom SoC. Is it possible for me to learn and acquire the development flow for less than 5K EUR budget – and if so, how should I proceed?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Fail to run the compiled MPS2+ project

    Hi,

    After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA.

    While the already downloaded image that arrives on the FPGA runs fine (i run the demo application), the image I compiled…

  • Could you recommend a specific FPGA board for ARM Cortex-M0 and Cortex-M3 implementation?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • The Cortex-M0 and Cortex-M3 processors are free for FPGA prototyping, but are they also free for IC prototyping?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • How to implement Cortex-M3 DesignStart Eval r0p0-02rel0 to Xilinx virtex 5 board?

    Hi.

    I came across Cortex-M3 DesignStart Eval r0p0-02rel0 implementing to the boards name of  ALTERA's MPS2+ from here https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system .

    But I'm looking for Xilinx board…

  • Program MPS2+ directly with Quartus programmer

    Is it possible to directly program the FPGA in the MPS2+ board with the Altera Quartus Programmer?

    As far as I understand is the MPS2+ 10 Pin FJTAG port not compatible to the Alter USB blaster.

    Is there another way to do this? 

  • What USB Blaster cable?

    Hello,

    I want to use an USB Blaster cable for rapid FPGA prototyping on the MPS2+. 

    The cables differ very much in price.  Is it recommended to buy an original Altera for over 200 Euro or can I use a cheaper nonamee one?

    Could you please recommend a cable…

  • Cortex M0 Designstart missing/unknown files and ignored includes

    Hi everyone,

    I'm using Windows 10 operating system(i couldn't know if this is relevant to second part of my problem) and I want to embed Cortex M0 Designstart Design Kit on a Xilinx FPGA board. I'm currently trying to synthesize (AT510) r1p0-00rel0…