Browse By Tags

Hello Everyone,

i want to use Designstart evl

&

i am not able to install these two software (GNU Binutils version 2.22. and GNU Make version 3.80.)  which is very important  for designstart evl .

So, Can you Please tell me how can i install or from where…

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

Hi, My name is Vedula. My back ground is 23 yrs in ASIC industry. Did Design/Verification/Validation. I want to get my hands dirty with DesignStart. I am interested in FPGA part. 

I Just downloaded Cortex-M1 DesignStart FPGA - Xilinx Pkg.

To start with…

Hi,

is there some guide which shows how to run a Keil hex mage for Cortex M3 in Modelsim?

To be more specific, I want to run an interactive simulation in Modelsim of my Cortex M3 design and associated software  to analyse  timings of CPU instructions and…

Hi,

I want to simulate CM3 Designstart with Modelsim.

When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:

** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…

Hello together, I am little bit confused regarding to the Cortex-M0DS comparability to Altera FPGAs.

On one hand, according to the information out of the white paper An introduction to ARM Cortex-M0 Design Start it must be possible to run the Cortex-M0…

Such as the title, I have a board of MPS3

I want to try to use the microphone to input the sound, then output through the speaker.

But I have been unable to find a way. I hope someone can point me out. Thank you.

Hi All,

I did not find QSPI models. Getting following errors. Could you please help me? Thank you.

[Project 1-19] Could not find the file 'C:/Users/srved/Downloads/ARM/AT472-BU-98000-r0p0-00rel0/AT472-BU-98000-r0p0-00rel0/hardware/m1_for_arty_s7/testbench…

Hi,

I want to buy above said board. But is based on Altera. I am not familiar with Altera. I am familiar with xilinx. Is there a similar board with Xilinx?

Thank you.

Regards,

Vedula.

I downloaded the example "Example CoreLink SSE-200 Subsystem_for_MPS3".

There seems to be no mention in the example how to write data to the SD card.

But I found that the example supports "stdio.h".

So I tried to specify the path with…

Hi.

TESTNAME=bootloader test sequence is in  BP210 CM3 test sequence,

In especially, we could find the below code,

then we got the below error message when we ran the simulation.

23490 ns UART: CMSDK Boot Loader 
27270 ns UART: - load flash 
45710…

Hello,

I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice…

In our product, cortex-m0 is internal digital block
1. After synthesis, inout ports such as P0, P1, will be inferred as tri-state logic(TLAT). Is it ok? or please provide the recommanded method.
2. For scan chain insertion, additional independent input…

For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea how to get the debugging to work. I defined the pins…

I want to run Cortex M-3 soft processor core on ZedBooard. I have downloaded the cortex M-3 IP core, created a deisgn by integrating Zynq Processor with Cortex M-3 processor and generated bitstreams.

I have also included the provided SW repository from…

I'm trying to load the block diagram for the arty a7 M1 example project. I get this error:

[BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'

Any thoughts on how to…

Hi,

I am trying to get familiarize with the SoC design provided with Desgin Start Cortex-M0 Eval version.

Here is my setup:

1. ARM Cortex-M0 core
2. Design Start Eval  with CMSDK used for SOC design.
3. Keil MDK – mdk_pro uvision V5.25.2.0
4. Vivado Tool used…

Hi,

I am trying to set up the synthesis environment for Cortex M0 and I have downloaded the FE part of the library from your website. However, according to the tech setup script (cmsdk_mcu_system_tech.tcl), it seems I am missing a folder which contains…

Hi,

I am trying to synthesize the M0 DesignStart but unfortunately I am having some trouble with the libraries. I was wondering what is the total power consumption according to the power report from Design Compiler, using the preset library (in implementation_tsmc_ce018fg…

Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…

Hi.

I started to play with DesignStart FPGA and implemented example design to a Xilinx Arty board. I successfully imported BSP to Keil, did some changes there and generated a new bitstream. Now I would like to start debug session in Keil, but I don't have…