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  • Fail to run the compiled MPS2+ project

    Hi,

    After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA.

    While the already downloaded image that arrives on the FPGA runs fine (i run the demo application), the image I compiled…

  • Simulate Cortex-M0 FPGA implementation in ModelSim

    Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
    I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

    I tried to start with Linux to see if at least the "make" commands are working. Problem…

  • Test Errors with DesignEval Kit

    I am currently in Evaluation phase of ARM Design Kits.

    I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide to compile the RTL and run the tests.

    But, unfortunately after compiling the RTL I am getting a stack…

  • Test Errors with DesignEval Kit (arm_cortex_m3_designstart_eval_rtl)

    I am currently in Evaluation phase of ARM Design Kits.

    I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

    to compile the RTL and run the tests.

    But, unfortunately after compiling the…

  • DesignStart Eval on Terasic DE10-Standard Board

    Hello,

    For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
    The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

    If I try to compile the ".sof" file of the Eval package in Quartus Prime…

  • how to implement mbed_blinky example on mps+2 board ?

    hi, GUys

       i buy a mps+2 board  and try to implement  mbed_blinky examples. but i meet issues on debugger and download axf files.

         now i can:

            1. export mbed_blinky examples for keil 

            2. compile success and generate axf file

            3. download fail

    …

  • First compile, verilog files missing

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

  • Cortex-M0 example system

    Hi,

    II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

    D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

  • Different Address of Reset Handler!

    Hi there,

    Why the address of reset handler is different from waveform and assembly code for hello testcase?

    This is obtained after compiling hello.c using Keil uVision 5.

    Reset_Handler
    0x000001c0: 4809 .H LDR r0,[pc,#36] ; [0x1e8] = 0x2a1
    0x000001c2:…