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  • does ARM Cortex-M0 DesignStart support SWD debugger?

    I am studying the ARM Cortex-M0 DesignStart. I found there are debug port SWDIOTMS and SWCLKTCK in the port list of cmsdk_mcu.v, and there are CPU options which defines the CPU's feature.

    I configured the parameter DBG = 1 in the cmsdk_mcu.v Line37…

    • 10402.zip

  • Cortex-M0 DesignStart Prototyping kit makefiles

    Unlike the Design kit makefiles, in which tool-chain (Keil, DS5 or GCC) can be chosen, the Prototyping kit makefiles uses only DS5.

    Is it possible to receive Prototyping kit makefiles that support tool-chain selection and in particular GCC?

  • Is there any documentation for design implementation on ARM Keil software?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • arm cortex m3 designstart debug with st_link.

    I download arm cortex m3 prototype  to the CYCLON 5 FPGA .Then use keil to debug the software but when click he debug button ,I encountered an error like the one shown above.

    I don't know how to solve the problem 

  • how to implement mbed_blinky example on mps+2 board ?

    hi, GUys

       i buy a mps+2 board  and try to implement  mbed_blinky examples. but i meet issues on debugger and download axf files.

         now i can:

            1. export mbed_blinky examples for keil 

            2. compile success and generate axf file

            3. download fail

    …

  • Program MPS2 with .axf file

    Hi,

    I am using the MPS2+ board to debug my DesignStart Cortex-M0. The core is up and running and now I want to program the onboard SRAM. On the SDCard I can see that \MB\HBIO263C\AN387\images.txt expects an axf file.

    Is it possible to generate an .axf…

  • Cortex-M0 example system

    Hi,

    II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

    D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

  • How to Debug CM3 DesignStart in the FPGA

    I use the ARM Cortex-M3 DesignStart Eval on the FPGA platform, I use J-link to download the program to the system but the system is not properly implemented. I downloaded the generated Hex file via J-link to the FPGA development board via Keil. Is the…

  • SWD issue in Cortex-m0

    We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside),  we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…

  • Different Address of Reset Handler!

    Hi there,

    Why the address of reset handler is different from waveform and assembly code for hello testcase?

    This is obtained after compiling hello.c using Keil uVision 5.

    Reset_Handler
    0x000001c0: 4809 .H LDR r0,[pc,#36] ; [0x1e8] = 0x2a1
    0x000001c2:…

  • Xilinx FPGA Block ROM is used as FLASH and how to load the program in to this?

    Hi,

    I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

    And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…

  • DesignStart Cortex-M1 non-module files issue with Vivado 2018.2 on Windows 10

    Hello all,

    I downloaded the Cortex-M1 DesignStart package for Xilinx FPGAs and followed the instructions given in the training videos. However, the HDL wrapper for the block diagram appears under "non-module files" in Vivado. Due to this I am not able…

  • FreeRTOS, Peripheral Modules with DesignStart FPGA

    Hello all,

    I have 2 questions regarding the Cortex M IP cores for Xilinx FPGAs (M1 on the Arty A7/S7, provided by ARM)

    1) I am new to ARM DesignStart and am looking to use freeRTOS with the Cortex M1 which project which has been provided for the Arty A7…

  • How to connect a ST-Link debugger to a Cortex-M1 design

    Hi.

    I started to play with DesignStart FPGA and implemented example design to a Xilinx Arty board. I successfully imported BSP to Keil, did some changes there and generated a new bitstream. Now I would like to start debug session in Keil, but I don't have…

  • Cortex M-3 on Zynq Evaluation and Development Board

    I want to run Cortex M-3 soft processor core on ZedBooard. I have downloaded the cortex M-3 IP core, created a deisgn by integrating Zynq Processor with Cortex M-3 processor and generated bitstreams.

    I have also included the provided SW repository from…