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  • First compile, verilog files missing

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

  • Modelsim for CM3 path error

    Hi,

    I want to simulate CM3 Designstart with Modelsim.

    When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:

    ** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…