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  • DesignStart FPGA 101: How to Design with Arm Cortex-M1

    July 11, 2019 03:00 PM to 07:00 PM Coordinated Universal Time

    GOWIN Semiconductor webinar series: Learn how to design with Cortex-M1 soft CPU IP into Gowin FPGAs Date: Thursday July 11 Times: 4pm and 8pm BST This webinar will introduce you to configuring GOWIN FPGA's with an Arm Cortex-M1 soft CPU IP, from...

  • Meet new Arm Innovator, Adam Taylor and his top 20 resources for FPGA developers

    As embedded and IoT applications continue to grow and push boundaries, there is a need for flexibility in product designs. This has resulted in a significant growth in application-optimized designs.

    The Xilinx product portfolio has been built to enable…

  • Cortex-M0 DesignStart processor size (FPGA)?

    Dear sirs,

    I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.

    When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.

    (I configure for using Spartan…

  • DesignStart Cortex-M1 non-module files issue with Vivado 2018.2 on Windows 10

    Hello all,

    I downloaded the Cortex-M1 DesignStart package for Xilinx FPGAs and followed the instructions given in the training videos. However, the HDL wrapper for the block diagram appears under "non-module files" in Vivado. Due to this I am not able…

  • External BRAM as I/D memory for Cortex-M1 DesignStart package for Xilinx FPGAs

    Hi,

    I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

    I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

  • How do di start?

    Hi, My name is Vedula. My back ground is 23 yrs in ASIC industry. Did Design/Verification/Validation. I want to get my hands dirty with DesignStart. I am interested in FPGA part. 

    I Just downloaded Cortex-M1 DesignStart FPGA - Xilinx Pkg.

    To start with…

  • Cortex-M1 for Xilinx FPGAs, max. clock frequency?

    Hello,

    I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice…

  • How to connect a ST-Link debugger to a Cortex-M1 design

    Hi.

    I started to play with DesignStart FPGA and implemented example design to a Xilinx Arty board. I successfully imported BSP to Keil, did some changes there and generated a new bitstream. Now I would like to start debug session in Keil, but I don't have…