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  • Cortex-M0 DesignStart processor size (FPGA)?

    Dear sirs,

    I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.

    When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.

    (I configure for using Spartan…

  • I am an FPGA SoC engineer and I want to create a custom SoC. Is it possible for me to learn and acquire the development flow for less than 5K EUR budget – and if so, how should I proceed?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Fail to run the compiled MPS2+ project

    Hi,

    After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA.

    While the already downloaded image that arrives on the FPGA runs fine (i run the demo application), the image I compiled…

  • Could you recommend a specific FPGA board for ARM Cortex-M0 and Cortex-M3 implementation?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • The Cortex-M0 and Cortex-M3 processors are free for FPGA prototyping, but are they also free for IC prototyping?

    This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

  • How to implement Cortex-M3 DesignStart Eval r0p0-02rel0 to Xilinx virtex 5 board?

    Hi.

    I came across Cortex-M3 DesignStart Eval r0p0-02rel0 implementing to the boards name of  ALTERA's MPS2+ from here https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system .

    But I'm looking for Xilinx board…

  • What USB Blaster cable?

    Hello,

    I want to use an USB Blaster cable for rapid FPGA prototyping on the MPS2+. 

    The cables differ very much in price.  Is it recommended to buy an original Altera for over 200 Euro or can I use a cheaper nonamee one?

    Could you please recommend a cable…

  • Cortex M0 Designstart missing/unknown files and ignored includes

    Hi everyone,

    I'm using Windows 10 operating system(i couldn't know if this is relevant to second part of my problem) and I want to embed Cortex M0 Designstart Design Kit on a Xilinx FPGA board. I'm currently trying to synthesize (AT510) r1p0-00rel0…

  • CM3 DesignStart Build warning messages with Quartus Prime 17.0.2

    Hi,

    I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

    I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

    Critical…

  • Has anyone had problems with implementing App Note AN387 using Cortex M0 r2p0 on a Cortex-M + dev board?

    All,

    I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

    In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

  • Simulate Cortex-M0 FPGA implementation in ModelSim

    Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
    I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

    I tried to start with Linux to see if at least the "make" commands are working. Problem…

  • Test Errors with DesignEval Kit

    I am currently in Evaluation phase of ARM Design Kits.

    I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide to compile the RTL and run the tests.

    But, unfortunately after compiling the RTL I am getting a stack…

  • Test Errors with DesignEval Kit (arm_cortex_m3_designstart_eval_rtl)

    I am currently in Evaluation phase of ARM Design Kits.

    I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

    to compile the RTL and run the tests.

    But, unfortunately after compiling the…

  • DesignStart Eval on Terasic DE10-Standard Board

    Hello,

    For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
    The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

    If I try to compile the ".sof" file of the Eval package in Quartus Prime…

  • DesignStart Pro: APB on FPGA via Quartus Prime

    Hello,

    I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…

  • arm cortex m3 designstart debug with st_link.

    I download arm cortex m3 prototype  to the CYCLON 5 FPGA .Then use keil to debug the software but when click he debug button ,I encountered an error like the one shown above.

    I don't know how to solve the problem 

  • First compile, verilog files missing

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

  • BME280 on DesignStart Eval via SPI Shield0

    Hello,

    I'm trying to connect the DesignStart Eval System to the BME280 Environmental Sensor via SPI. I used the SPI Shield0 Pins (EXP[11 to 14]) to set the connection and activated alternate functions in uVision for these pins. But how can I set up the…

  • How to Debug CM3 DesignStart in the FPGA

    I use the ARM Cortex-M3 DesignStart Eval on the FPGA platform, I use J-link to download the program to the system but the system is not properly implemented. I downloaded the generated Hex file via J-link to the FPGA development board via Keil. Is the…

  • Cortex-M0 DesignStart Eval

    Hi

    I have download the Cortex-M0 DesignStart Eval file (AT510-MN-80001-r2p0-00rel0),
    and read the ARM FPGA board (MPS2+) datasheet.

    The MPS2+ have many peripheral devices but we don't need it,
    so we want made a platform for our use.

    The user guide…

  • M0: remove PMU/CG

    Hi,

    I am using Cortex-M0 DesignStart Pro. I want to port the Model to FPGA, where I do not need any clock gating or power management. Is there a way to remove the PMU completely?

    Best regards,
    LeChuck

  • SWD issue in Cortex-m0

    We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside),  we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…

  • Xilinx FPGA Block ROM is used as FLASH and how to load the program in to this?

    Hi,

    I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

    And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…

  • DesignStart Cortex-M1 non-module files issue with Vivado 2018.2 on Windows 10

    Hello all,

    I downloaded the Cortex-M1 DesignStart package for Xilinx FPGAs and followed the instructions given in the training videos. However, the HDL wrapper for the block diagram appears under "non-module files" in Vivado. Due to this I am not able…