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  • Cortex-M0 DesignStart processor size (FPGA)?

    Dear sirs,

    I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.

    When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.

    (I configure for using Spartan…

  • Has anyone had problems with implementing App Note AN387 using Cortex M0 r2p0 on a Cortex-M + dev board?

    All,

    I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

    In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

  • Simulate Cortex-M0 FPGA implementation in ModelSim

    Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
    I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

    I tried to start with Linux to see if at least the "make" commands are working. Problem…

  • Modelsim for CM3 path error

    Hi,

    I want to simulate CM3 Designstart with Modelsim.

    When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:

    ** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…

  • Cortex M3 on Arty A35T with Vivado 2018.3 Windows 10

    Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…