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  • Research with the industry-leading IP

    For nearly a decade now, Arm DesignStart has enabled academics to access Arm IP for teaching and research purposes. Many academics around the world have taught SoC design to thousands of students, basing their course on the Arm Education Kit based on…

  • How to implement Cortex-M3 DesignStart Eval r0p0-02rel0 to Xilinx virtex 5 board?

    Hi.

    I came across Cortex-M3 DesignStart Eval r0p0-02rel0 implementing to the boards name of  ALTERA's MPS2+ from here https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system .

    But I'm looking for Xilinx board…

  • What is the maximum running frequency for Cortex-M3 on TSMC 40nm process?

  • Are the CoreSight Debug components made available through DesignStart also?

  • Does the Cortex-M0 include any security options?

  • Will there be tutorials, videos that explain more details on the design process? Is there a possibility of simulation/test for effectiveness?

  • What are the approximate numbers for gates required for a Cortex-M0 and Cortex-M3 CPU?

  • We are looking to build a new FPU.  Can we get hooks to build this FPU into the SoC?

  • For IoT implementation, which is better: the Cortex-M0 or Cortex-M3 - and why?

  • What ASIL level can be achieved with the Cortex-M3 processor?

  • Is there any documentation for design implementation on ARM Keil software?

  • The Cortex-M0 and Cortex-M3 processors are free for FPGA prototyping, but are they also free for IC prototyping?

  • Can the DesignStart Eval RTL project provided be modified? For example, to add new ports or remove unused ones for customization.

  • Fab costs prohibit many start-ups and small companies to pursue custom SoC development. Does ARM have any plans to help companies on this, maybe with some fab partners similar to the design partners

  • If I am an individual how can I apply for the DesignStart program and get a prototype?

  • Are DesignStart Pro royalties based on the number of cores instantiated in single chip? If so, what about permanent lockstep configurations?

  • Could you recommend a specific FPGA board for ARM Cortex-M0 and Cortex-M3 implementation?

  • Is the DesignStart Eval compatible with heterogeneous multi-core design, e.g. Cortex-M0 with Cortex-M3?

  • Enhance your product with industry-leading processors – for no upfront license fee

    The Arm System Design Kits (also known as Arm CoreLink System Design Kits or SDKs) have been rebranded into Arm Corstone foundation IP.

    The appeal of intelligence in everyday products is driving the demand for smart sensors and smart analog SoCs (system…

  • Assuming knowledge of standard off-the-shelf SoC and FPGA designs, what big challenges exists for an integrated solution?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • How is the SoC-based design validated? Is it done against some specifications or compliance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Can SoC Verification be automated using Machine Learning? If so, how can we ensure 100% functional coverage?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • Is it possible to interface a high frequency sensor-signal output from an analog ASIC chip (e.g. several Kilohertz) using Cortex-M?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

  • With regards to custom SoCs, what is the trade-off between low cost and performance?

    This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.